1. Field of the Invention
This invention relates to clock signal multiplexers.
2. Description of the Prior Art
The need to multiplex a plurality of clock signals together, that is, to combine the clock signals serially into a single channel by selectively passing one of the clock signals to the exclusion of the others, arises in various circuits. Consider, for example, a digital video tape recorder which is deriving four binary data signals via respective reproducing heads, where all four data signals are to be stored a single memory, such as a field store. In this case, a respective clock signal will be derived from each reproduced data signal for use in controlling the memory when that data signal is to be stored. All four clock signals are of the same frequency, and ideally they will remain in a constant phase relationship, but in practice, due to jitter, this may not be so, and as a consequence there may be a clash of control of the memory.
In these and other circuits there is, therefore, a requirement for a clock signal multiplexer capable of multiplexing a plurality of clock signals of the same frequency but differing phases, to provide a signal output clock signal, with the assurance that the output clock signal will always be continuous, and will always contain complete clock cycles and be glitch-free. Previously proposed clock signal multiplexers, such as simple switching devices, do not provide these assurances.